Applicability conditions, architecture, and quantitative models of a hardware second layer in two-layer distributed event processing

Abstract

Relevance. Events that share an aggregate identifier are functionally dependent: they must be applied to the projection state strictly in order, so the throughput of one aggregate is limited by a single serial executor, horizontal scaling does not raise this per-key ceiling, and software executors additionally exhibit pause-driven latency tails. The aim of the article is to determine the formal conditions under which the second (projection) layer of a two-layer distributed event-processing architecture should be computed in reconfigurable hardware rather than in software, and to construct and validate quantitative models of such an implementation. Tasks: formalization of the projection as a per-key state transducer; derivation of applicability attributes and decision conditions; specification of the reference architecture of the serialization layer, the hardware core, and the host software; construction and validation of models of throughput, latency, cost, conflated egress, and checkpointing. Methods: the theory of cost register automata and join-semilattices, queueing theory, renewal theory, the Young-Daly checkpoint model, and discrete-event simulation. Scientific novelty: for the first time, a formal applicability framework – six attributes with connecting propositions and four decision conditions – is proposed that determines exactly which event-processing algorithms benefit from a hardware projection layer; for the first time, an exact closed-form expression is obtained for the egress rate and the mean age of information of a rate-limited last-value cache fed by a Poisson update stream; the two-layer in-memory architecture is improved by relocating the projection computation into a hardware core with a fixed-offset serialization contract; the quantitative models of two-layer event processing are further developed for the hardware substrate. Practical significance: decision surfaces and break-even curves that allow practitioners to justify the choice between the hardware layer, tuned software, and stream frameworks, together with implementation principles and a verification protocol that reduce the risk of the hardware path. Results: a single hardware accelerator sustains a high volume of small-packet events per second—significantly outperforming conventional processor cores and standard software serial rates; it maintains ultra-low and predictable tail latencies while eliminating pause-afflicted software spikes; it achieves high cost-efficiency compared to software alternatives at scale under current cloud pricing; and it substantially reduces auction fan-out egress while maintaining a bounded mean staleness.Conclusions: the transfer of the second layer into hardware is a contract of six attributes; where the contract holds, the gains are structural rather than incremental, and where it fails, stream frameworks remain the right substrate. All closed forms are validated by simulation with a negligible worst-case relative error.